VLSI Design Basic Flow

 The below diagram shows the basic VLSI flow:

RTL Design:

• RTL Specification: The RTL engineer takes the concept+market research (Blueprint) from the customer and converts it into the HDL code (Verilog or VHDL).
• Functional Verification::The RTL team verify the HDL code such that it meets the specification of the customer

Logic Design:

• Synthesis: Verified RTL code is given to the synthesis team and they convert it into gate-level netlist (Verilog netlist)
• Logical Equivalence Check: Now they do LEC check to ensure that the logic is functions correctly.

Physical Design:

•  Floor Planning: Floorplanning is a process where the PD engineer place the macros, ios, and other instances at their specific orientation and locations.
• Placement: Placement of the standard cells is done here, standard cells are placed in cell rows inside the core area. 
• Clock Tree Synthesis: The clock tree is built in the design.
• Routing: Here the net is routed in the design. 
• Tape Out: The final step in the PD flow where the design is tape out and layout is given to the foundry.