Sanity Checks

The main Importance of doing the sanity checks in the physical design flow is to ensure that there is no problem arising in the latter stage relating to these checks.

List of the sanity checks that were carried out on physical design flow.

• check_library
• check_design
• check_timing
• check_legality
• report_timing
• report_qor
• report_constraint

check_library: It performs consistency checks between logical and physical libraries. To ensure that each cell that is defined in the netlist has its corresponding physical, timing, and logical information defined in libraries.

check_design: This check is done to report the design information like total area of the design, inst count in the design, total number ports/pins in the design, undriven input ports/pins, unloaded output ports/pins, net with multiple drivers, etc.

check_timing: PnR tools can't optimize the paths which are unconstrained. So we have to check any unconstrained paths that exist in our design. The check_timing command will report the unconstrained paths. if there are any unconstrained paths in our design, run the report_timing command to verify whether the unconstrained paths are false paths.

check_ligality: It reports the violations regarding cell overlap and orientation.

report_timing: Command reports the timing information for the current design. By default, the report_timing reports the single worst (nworst 1) setup path in each clock group.

report_qor: Command reports the QoR of the current design. It includes each path group separately the worst negative slack, total negative slack, the number of violating paths in each path group, in addition to this it also contains design-related info such as total area of design, number of combinational and sequential cells, etc.

report_constraint: command reports the constraint violation, by how much it violated and worst violating object.