Synthesis

Synthesis is a process of converting RTL verified code to technology-specific gate-level netlist.

Synthesis goal

• To get a gate-level netlist
• Inserting clock gates
• Logic optimization
• Inserting DFT logic
• Logic equivalence between RTL code and netlist should be maintained

Input files required for the synthesis

Tech-related files:

• .tf- technology-related information.
• .lib-timing info of standard cell & macros

Design related:

• .v- RTL code.
• SDC- Timing constraints.
• UPF- power intent of the design.
• Scan config- Scan-related info like scan chain length, scan IO, which flops are to be considered in the scan chains.

For Physical aware:

• RC co-efficient file (tluplus).
• LEF/FRAM- abstract view of the cell.
• Floorplan DEF- locations of IO ports and macros.

Synthesis steps

                              Fig1: Synthesis Flow

Analyze and Elaborate

Analyze

Checks syntax on RTL code and generates immediate files.

Elaborate

Brings all lower-level blocks into synthesis tool.

All the codes and arithmetic operators are converted into Gtech and DW (Design Ware) components. These are technology-independent libraries.

Gtech- contains basic logic gates & flops.

DesignWare- contains complex cells like FIFO, counters ect.

Elaborate performs following tasks:

• Analyses design hierarchy.
• Removes empty switches and dead branches.
• Executes initial commands.
• Detects asynchronous reset.
• Converts decision trees to mux.
• Converts synchronous to Dlatch/DFF.
• FSM pass
• Detects FSM logic and extracts the no of input, output bits, and state bits.
• Converts FSM logic to basic logic.
• Memory pass
• Merging DFF to memory write(memwr) and memory read (memrd)
• Consolidating memwr/memrd cells
• Generate memory (mem) cells
• Mapping mem cells to basic logic

Import constraints and UPF

Once the design is extracted in the form of technology-independent cells, timing constraints are imported from the SDC file.

If the design consists of multiple power domains, (voltage area) then using the UPF power domains, isolation cells, level shifters, power switches, retention flops are placed.

Clock gating

Due to the high switching activity of the clock, a lot of dynamic power is consumed. One of the techniques to lower the dynamic power is clock gating. 

Compile

• Performs Boolean optimization.
• Maps all the cells to technology libraries.
• Performs logic and design optimization.

Optimization

• Logic optimization
• Constant folding
• Detect identical cells
• Optimize mux(dead branches in mux)
• consolidate mux and reduce inputs(many to single)
• Remove DFF with a constant value
• Reduce word size of the cells
• Remove unused cells and wires
• Design optimization
• Reduce TNS and WNS
• Power Optimization
• Area Optimization
• Meet the timing DRV’s
• incremental clock gating

DFT (Design for Testing) insertion

• DFT circuits are used for testing each and every node in the design.
• More the numbers of nodes that can be tested with some targeted pattern, more is the coverage.
• To get more coverage the design needs to be more controllable and observable.
• For the design to be more controllable we need more control points (mux through which alternate path is provided to propagate pattern).
• For the design to be more observable we need more observe points (A scan-able flop that observes the value at that node).
• Scan mode is used to test stuck-at faults and manufactured devices for the delay.
• Scan mode is done using scan chains
• Scan chains are part of scan-based designs to propagate the test data.
• By having scan chains, the design can be more controllable and observable.
• Each scan chain inputs the pattern through scan input and outputs the pattern through scan output.
• Scan chain consists of scan flops where the output of scan flops is directly connected to scan inputs of the flops.

Compile incremental

• Technology mapping of DFT circuit
• Optimization of the design

Outputs of Synthesis

• Gate level netlist
• SDC
• UPF
• ScanDEF

Checklist at post-synthesis

• Check if the RTL and netlist are logically equivalent (LEC/FM).
• Check if SDC and UPF are generated after synthesis and also check their completeness.

Checks related to timing

• Combinational loops
• Un-clocked registers
• unconstrained IO’s
• IO delay missing
• Un-expandable clocks
• Master-slave separation
• multiple clocks

Checks related to design

• Floating pins
• multi driven inputs
• un-driven inputs
• un-driven outputs
• normal cells in the clock path
• pin direction mismatch
• don’t use cells

VLSI Design Basic Flow

 The below diagram shows the basic VLSI flow:

RTL Design:

• RTL Specification: The RTL engineer takes the concept+market research (Blueprint) from the customer and converts it into the HDL code (Verilog or VHDL).
• Functional Verification::The RTL team verify the HDL code such that it meets the specification of the customer

Logic Design:

• Synthesis: Verified RTL code is given to the synthesis team and they convert it into gate-level netlist (Verilog netlist)
• Logical Equivalence Check: Now they do LEC check to ensure that the logic is functions correctly.

Physical Design:

•  Floor Planning: Floorplanning is a process where the PD engineer place the macros, ios, and other instances at their specific orientation and locations.
• Placement: Placement of the standard cells is done here, standard cells are placed in cell rows inside the core area. 
• Clock Tree Synthesis: The clock tree is built in the design.
• Routing: Here the net is routed in the design. 
• Tape Out: The final step in the PD flow where the design is tape out and layout is given to the foundry. 

Sanity Checks

The main Importance of doing the sanity checks in the physical design flow is to ensure that there is no problem arising in the latter stage relating to these checks.

List of the sanity checks that were carried out on physical design flow.

• check_library
• check_design
• check_timing
• check_legality
• report_timing
• report_qor
• report_constraint

check_library: It performs consistency checks between logical and physical libraries. To ensure that each cell that is defined in the netlist has its corresponding physical, timing, and logical information defined in libraries.

check_design: This check is done to report the design information like total area of the design, inst count in the design, total number ports/pins in the design, undriven input ports/pins, unloaded output ports/pins, net with multiple drivers, etc.

check_timing: PnR tools can't optimize the paths which are unconstrained. So we have to check any unconstrained paths that exist in our design. The check_timing command will report the unconstrained paths. if there are any unconstrained paths in our design, run the report_timing command to verify whether the unconstrained paths are false paths.

check_ligality: It reports the violations regarding cell overlap and orientation.

report_timing: Command reports the timing information for the current design. By default, the report_timing reports the single worst (nworst 1) setup path in each clock group.

report_qor: Command reports the QoR of the current design. It includes each path group separately the worst negative slack, total negative slack, the number of violating paths in each path group, in addition to this it also contains design-related info such as total area of design, number of combinational and sequential cells, etc.

report_constraint: command reports the constraint violation, by how much it violated and worst violating object.